Before an integrated circuit (IC) component, such as a processor or a main memory device, may be used in a system, proper functionality and timing within each input/output (I/O) buffer of the component needs to be verified. This may be accomplished by placing the component on a so called semiconductor tester which has a channel for each I/O pin of the component. Test patterns are then communicated back and forth between the component and the tester on each pin, and the proper functionality and timing of an I/O buffer is verified by comparing an actual received or driven test value with an expected received or driven test value.
In modern, high performance electronic systems, however, there is also a need to test the system or platform of which the IC component is a part. Traditionally, probing techniques have been used for such a purpose, where a probe is used to pick up signals that are being driven between IC components of the system. However, that technique is proving to be less reliable as signal switching speeds increase. To reduce the need for such probing, built-in self test circuitry can be added inside each IC component, to verify, at speed, inter-component communications in the system.
In U.S. Pat. No. 6,477,674 assigned to the same assignee as that of this application, namely Intel Corp., an I/O loopback test is described for self testing the I/O buffers of an IC component using switching signals (hence the use of “AC”). Such a test may be carried out by driving test data out of the IC component through an output portion of an I/O buffer. Subsequently, the data is driven back through an input portion of the I/O buffer. A comparison is then made to verify that the correct data has been received. This helps verify whether the input and output portions of each I/O buffer associated with a pin of the component are functioning properly, without the need for external probing or connecting with a tester. The I/O circuitry thus tests itself, independent of the component's core logic. In that instance, an I/O buffer is described as having an I/O pad, an output driver, an input receiver, and a test circuit that generates test pattern signals when the I/O buffer is operating in a test mode. A latch is used to store an error signal that is generated as part of the test. The latch may be a boundary scan latch whose contents may be examined by other IC components of the system or by an external tester, as part of a boundary scan-chain (where test values from multiple IC components are shifted out serially). Using such a technique, test pattern values may be loaded into the latch one bit at a time, through a serial scan in port, and read out of the latch serially through a scan out port.